View AOZ1037_5854889.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.1 september 2010 www.aosmd.com page 1 of 14 AOZ1037 ezbuck? 5a synchron ous buck regulator general description the AOZ1037 is a high efficiency, simple to use, 5a synchronous buck regulator. the AOZ1037 works from a 4.5v to 18v input voltage range, and provides up to 5a of continuous output current with an output voltage adjustable down to 0.8v. the AOZ1037 comes in an exposed pad so-8 packages and is rated over a -40c to +85c ambient temperature range. features z 4.5 to 18v operating input voltage range z synchronous rectification: 55m ? internal high-side switch and 19m ? internal low-side switch z high efficiency: up to 95% z internal soft start z active high power good state z output voltage adjustable to 0.8v z 5a continuous output current z fixed 500khz pwm operation z cycle-by-cycle current limit z pre-bias start-up z short-circuit protection z thermal shutdown z exposed pad so-8 package applications z point of load dc/dc conversion z lcd tvs z set top boxes z dvd / blu-ray players/recorders z cable modems z pcie graphics cards z telecom/networking/datacom equipment typical application figure 1. 3.3v/5a synchronous buck regulator lx vin vin vout fb pgnd en comp agnd c2, c3 22f r1 r2 c c r c c1 22f l1 4.7h AOZ1037 pgood r3 5v
AOZ1037 rev. 1.1 september 2010 www.aosmd.com page 2 of 14 ordering information aos green products use reduced levels of halogens, and are also rohs compliant. please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information. pin configuration pin description part number ambient temperature range package environmental AOZ1037pi -40c to +85c epad so-8 green product 1 2 3 4 pgnd vin a gnd fb exposed pad so-8 (top view) pad (lx) nc pgood en comp 8 7 6 5 pin number pin name pin function 1 pgnd power ground. pgnd needs to be electrically connected to agnd. 2v in supply voltage input. when v in rises above the uvlo threshold and en is logic high, the device starts up. 3 agnd analog ground. agnd is the reference point for controller section. agnd needs to be electrically connected to pgnd. 4 fb feedback input. the fb pin is used to set the output voltage via a resistor divider between the out- put and agnd. 5 comp external loop compensation pin. connect a rc network between comp and agnd to compen- sate the control loop. 6 en enable pin. pull en to logic high to enable the device. pull en to logic low to disable the device. if on/off control is not needed, connect it to v in and do not leave it open. 7 pgood power good output. pgood is an open-drain out put that indicates the st atus of output voltage. pgood is pulled low when output is below 90% of the normal regulation. 8 nc no connect. pin 8 is not internally connected. pad lx switching node. lx is the drain of the internal pfet. lx is used as the thermal pad of the power stage.
AOZ1037 rev. 1.1 september 2010 www.aosmd.com page 3 of 14 block diagram absolute maximum ratings exceeding the absolute maximum ratings may damage the device. note: 1. devices are inherently esd s ensitive, handling precautions are required. human body model rating: 1.5k ? in series with 100pf. recommended operating conditions the device is not guaranteed to operate beyond the maximum recommended operating conditions. note: 2. the value of ja is measured with the device mounted on 1-in 2 fr-4 board with 2oz. copper, in a still air environment with t a = 25c. the value in any given application depends on the user's specific board design. 500khz oscillator agnd pgnd vin en fb comp lx otp internal +5v ilimit pwm control logic 5v ldo regulator uvlo & por softstart reference & bias 0.8v q1 q2 pwm comp level shifter + fet driver isen eamp 0.2v + ? + ? + ? + ? + short circuit detection comparator 0.72v ? + pgood parameter rating supply voltage (v in ) 20v lx to agnd -0.7v to v in +0.3v lx to agnd 23v (<50ns) en to agnd -0.3v to v in +0.3v fb to agnd -0.3v to 6v comp to agnd -0.3v to 6v pgnd to agnd -0.3v to +0.3v junction temperature (t j ) +150c storage temperature (t s ) -65c to +150c esd rating (1) 2.0kv parameter rating supply voltage (v in ) 4.5v to 18v output voltage range 0.8v to v in ambient temperature (t a ) -40c to +85c package therma l resistance exposed pad so-8 ( ja ) (2 ) 50c/w
AOZ1037 rev. 1.1 september 2010 www.aosmd.com page 4 of 14 electrical characteristics t a = 25c, v in = v en = 12v, v out = 3.3v unless otherwise specified (3 ) note: 3. specification in bold indicate an ambient temperature range of -40c to + 85c. these specifications are guaranteed by design. symbol parameter conditions min. typ. max. units v in supply voltage 4.5 18 v v uvlo input under-voltage lockout threshold v in rising v in falling 4.1 3.7 v i in supply current (quiescent) i out = 0, vfb = 1.2v, v en > 1.2v 1.6 2.5 ma i off shutdown supply current v en = 0v 1.0 10 a v fb feedback voltage t a = 25c 0.788 0.8 0.812 v load regulation 0.5 % line regulation 1.0 % i fb feedback voltage input current 200 na enable v en en input threshold off threshold on threshold 2 0.6 v v hys en input hysteresis 100 mv modulator f o frequency 400 500 600 khz d max maximum duty cycle 100 % t on_min minimum on time 150 ns g vea error amplifier voltage gain 500 v / v g ea error amplifier transconductance 200 a / v protection i lim current limit 5.8 6.5 a over-temperature shutdown limit t j rising t j falling 150 100 c t ss soft start interval 3ms power good v olpg pg low voltage i ol = 1ma 0.6 v pg leakage 1a v pgl pg threshold voltage 87 90 92 %vo pg threshold voltage hysteresis 3 % t pg pg delay time 128 s pwm output stage high-side switch on-resistance v in = 12v v in = 5v 55 75 m ? low-side switch on-resistance v in = 12v v in = 5v 19 23 m ?
rev. 1.1 september 2010 www.aosmd.com page 5 of 14 AOZ1037 typical performance characteristics circuit of figure 1. t a = 25c, v in = v en = 12v, v out = 3.3v unless otherwise specified. light load operation 2ms/div start up to full load 1ms/div full load (ccm) operation 1 s/div short circuit protection 50 s/div short circuit recovery 1ms/div vin ripple 0.1v/div vo ripple 20mv/div il 1a/div vlx 10v/div vin ripple 0.1v/div vo ripple 20mv/div il 1a/div vlx 10v/div vin 10v/div vo 2v/div lin 1a/div lx 10v/div vo 2v/div il 2a/div lx 10v/div vo 2v/div il 2a/div
rev. 1.1 september 2010 www.aosmd.com page 6 of 14 AOZ1037 efficiency efficiency (v in = 12v) vs. load current 40% 50% 60% 70% 80% 90% 100% 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 load current (a) efficiency (%) 5v output 3.3v output 1.8v output 1.2v output efficiency (v in = 5v) vs. load current 40% 50% 60% 70% 80% 90% 100% 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 load current (a) efficiency (%) 3.3v output 1.8v output 1.2v output
rev. 1.1 september 2010 www.aosmd.com page 7 of 14 AOZ1037 detailed description the AOZ1037 is a current-mode step down regulator with integrated high-side pmos switch and a low-side nmos switch. it operates from a 4.5v to 18v input voltage range and supplies up to 5a of load current. features include enable control, power-on reset, input under voltage lockout, output over voltage protection, acti ve high power good state, fixed internal soft-start and thermal shut down. the AOZ1037 is available in exposed pad so-8 package. enable and soft start the AOZ1037 has an internal soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. a soft start process begins when the input voltage rises to 4.1v and voltage on en pin is high. in the soft start process, the output voltage is typically ramped to regulation voltage in 3ms. the 3ms soft start time is set internally. the en pin of the AOZ1037 is active high. connect the en pin to v in if the enable function is not used. pulling en to ground will disable the AOZ1037. do not leave it open. the voltage on the en pin must be above 2v to enable the AOZ1037. when voltage on the en pin falls below 0.6v, the AOZ1037 is disabled. if an application circuit requires the AOZ1037 to be disabled, an open drain or open collector circuit should be used to interface to the en pin. power good the output of power-good is an open drain n-channel mosfet, which supplies an active high power good stage. a pull-up resistor (r3) should connect this pin to a dc poer trail with maximum voltage no higher than 6v. the AOZ1037 monitors the fb voltage: when fb pin voltage is lower than 90% of the normal voltage, n- channel mosfet turns on and the power-good pin is pulled low, which indicate s the power is abnormal. steady-state operation under steady-state conditions, the converter operates in fixed frequency and continuous-conduction mode (ccm). the AOZ1037 integrates an internal p-mosfet as the high-side switch. inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power mosfet. output voltage is divided down by the external voltage divider at the fb pin. the difference of the fb pin voltage and reference is amplified by the internal transconductance error amplifier. the error voltage, which shows on the comp pin, is compared against the current signal, which is sum of inductor current signal and ramp compensation signal, at the pwm comparator input. if the current signal is less than the error voltage, the internal high-side switch is on. the inductor current flows from the input through the inductor to the output. when the current signal exceeds the error voltage, the high-side switch is off. the inductor current is freewheeling through the internal low-side n-mosfet switch to output. the internal adaptive fet driver guarantees no turn on overlap of both high-side and low-side switch. comparing with regulators using freewheeling schottky diodes, the AOZ1037 uses freewheeling nmosfet to realize synchronous rectification. it greatly improves the converter efficiency and reduces power loss in the low-side switch. the AOZ1037 uses a p-channel mosfet as the high- side switch. it saves the bootstrap capacitor normally seen in a circuit which is using an nmos switch. switching frequency the AOZ1037 switching frequency is fixed and set by an internal oscillator. the pr actical switching frequency could range from 400 khz to 600 khz due to device variation. light load mode the AOZ1037 includes is a pulse-skip architecture for light load operation, enabling increased efficiency during standby. under heavy loads, the controller operates in a standard sy nchronous mode using the high-side pmos as control fet and low-side nmos as synchronous rectifier nmos. during light loads, the controller automatically switches to a non-synchronous mode using the high-side pmos as control fet and the integrated diode as freewheeling rectifier diode. output voltage programming output voltage can be set by feeding back the output to the fb pin by using a resistor divider network. in the application circuit shown in figure 1, the resistor divider network includes r 1 and r 2 . usually, a design is started by picking a fixed r 2 value and calculating the required r 1 with equation below: v o 0.8 1 r 1 r 2 ------ - + ?? ?? ?? =
AOZ1037 rev. 1.1 september 2010 www.aosmd.com page 8 of 14 some standard value of r1, r2 and most used output voltage values are listed in table 1. table 1. the combination of r 1 and r 2 should be large enough to avoid drawing excessive current from the output, which will cause power loss. protection features the AOZ1037 has multiple protection features to prevent system circuit damage under abnormal conditions. over current protection (ocp) the sensed inductor current si gnal is also used for over current protection. since the AOZ1037 employs peak current mode control, the comp pin voltage is proportional to the peak inductor current. the comp pin voltage is limited to be between 0.4v and 2.5v internally. the peak inductor current is automatically limited cycle by cycle. when the output is shorted to ground under fault conditions, the inductor current decays very slow during a switching cycle because of v o = 0v. to prevent catastrophic failure, a secondary current limit is designed inside the AOZ1037. the measured inductor current is compared against a preset voltage which represents the current limit. when the outpu t current is more than current limit, the high side sw itch will be turned off and en pin will be pulled down. the converter will initiate a soft start once the over-current condition disappears. power-on reset (por) a power-on reset circuit monitors the input voltage. when the input voltage exceeds 4.1v, the converter starts operation. when input voltage falls below 3.7v, the converter will be shut down. thermal protection an internal temperature sensor monitors the junction temperature. it shuts down the internal control circuit and high side pmos if the junction temperature exceeds 150c. the regulator will rest art automatica lly under the control of soft-start circuit when the junction temperature decreases to 100c. application information the basic AOZ1037 application circuit is show in figure 1. component selection is explained below. input capacitor the input capacitor must be connected to the v in pin and pgnd pin of AOZ1037 to maintain steady input voltage and filter out the pulsing input current. the voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage. the input ripple voltage can be approximated by equation below: since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. for a buck circuit, the rms value of input capacitor current can be calculated by: if we let m equal the conversion ratio: the relationship between the input capacitor rms current and voltage conversion ratio is calculated and shown in figure 2 below. it can be seen that when v o is half of v in , c in is under the worst current stress. the worst current stress on c in is 0.5 x i o . v o (v) r 1 (k ? ) r 2 (k ? ) 0.8 1.0 open 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.1 10 5.0 52.3 10 v in i o fc in ----------------- 1 v o v in -------- - ? ?? ?? ?? v o v in -------- - = i cin_rms i o v o v in -------- - 1 v o v in -------- - ? ?? ?? ?? = v o v in -------- - m =
AOZ1037 rev. 1.1 september 2010 www.aosmd.com page 9 of 14 figure 2. i cin vs. voltage conversion ratio for reliable operation and best performance, the input capacitors must have current rating higher than i cin_rms at worst operating conditions. ceramic capacitors are preferred for input capacitors because of their low esr and high current rating. depending on the application circuits, other low esr tantalum capacitor may also be used. when selecting ceramic capacitors, x5r or x7r type dielectric ceramic capa citors should be used for their better temperature and voltage characteristics. note that the ripple current rating from capacitor manufactures are based on certain amount of life time. further de-rating may be necessary in practical design. inductor the inductor is used to supply constant current to output when it is driven by a switching voltage. for given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is: the peak inductor current is: high inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. low ripple current reduces inductor core losses. it also reduces rms current through inductor and switches, which results in less conduct ion loss. usually, peak to peak ripple current on inductor is designed to be 20% to 30% of output current. when selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. the inductor takes the highest current in a buck circuit. the conduction loss on inductor need to be checked for thermal and efficiency requirements. surface mount inductors in different shape and styles are available from coilcraft, el ytone and murata. shielded inductors are small and radiate less emi noise. but they cost more than unshielded inductors. the choice depends on emi requirement, price and size. output capacitor the output capacitor is selected based on the dc output voltage rating, output ripple voltage specification and ripple current rating. the selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple. de-rating needs to be considered for long term reliability. output ripple voltage specification is another important factor for selecting the output capacitor. in a buck converter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and esr. it can be calculated by the equation below: where, c o is output capacitor value, and esr co is the equivalent series resistance of the output capacitor. when low esr ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switching frequency dominates. output ripple is mainly caused by capacitor value and inductor ripple current. the output ripple voltage calculation can be simplified to: if the impedance of esr at switching frequency dominates, the output ripple voltage is mainly decided by capacitor esr and inductor ripple current. the output ripple voltage calculation can be further simplified to: 0 0.1 0.2 0.3 0.4 0.5 0 0.5 1 m i cin_rms (m) i o i l v o fl ---------- - 1 v o v in -------- - ? ?? ?? ?? = i lpeak i o i l 2 -------- + = v o i l esr co 1 8 fc o ------------------------- + ?? ?? = v o i l 1 8 fc o ------------------------- = v o i l esr co =
AOZ1037 rev. 1.1 september 2010 www.aosmd.com page 10 of 14 for lower output ripple voltage across the entire operating temperature range, x5r or x7r dielectric type of ceramic, or other low esr tantalum are recommended to be used as output capacitors. in a buck converter, out put capacitor current is continuous. the rms current of output capacitor is decided by the peak to peak inductor ripple current. it can be calculated by: usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. when the buck inductor is selected to be very small and inductor ripple current is high, output capacitor could be overstressed. external schottky diode for high input operation when v in is higher than 16v, an external 1a schottky diode is required between lx and pgnd for proper operation. loop compensation the AOZ1037 employs peak current mode control for easy use and fast transient response. peak current mode control eliminates the doubl e pole effect of the output l&c filter. it greatly simp lifies the compensation loop design. with peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. the pole is dominant pole can be calculated by: the zero is a esr zero due to output capacitor and its esr. it is can be calculated by: where; c o is the output filter capacitor, r l is load resistor value, and esr co is the equivalent series resistance of output capacitor. the compensation design is actually to shape the converter control loop transfer function to get desired gain and phase. several different types of compensation network can be used for the AOZ1037. for most cases, a series capacitor and resistor network connected to the comp pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. in the AOZ1037, fb pin and comp pin are the inverting input and the output of internal error amplifier. a series r and c compensation network connected to comp provides one pole and one zero. the pole is: where; g ea is the error amplifier transconductance, which is 200 x 10 -6 a/v, g vea is the error amplifier voltage gain, which is 500 v/v, and c 2 is the compensation capacitor in figure 1. the zero given by the external compensation network, capacitor c 2 and resistor r 3 , is located at: to design the compensation circuit, a target crossover frequency f c for close loop must be selected. the system crossover frequency is where control loop has unity gain. the crossover is the also called the converter bandwidth. generally a higher bandwidth means faster response to load transient. however, the bandwidth should not be too high because of system stability concern. when designing the comp ensation loop, converter stability under all line and load condition must be considered. usually, it is recommended to set the bandwidth to be equal or less than 1/10 of switching frequency. the AOZ1037 operates at a frequency range from 400khz to 600khz. it is recommended to choose a crossover frequency equal or less than 40khz. the strategy for choosing r c and c c is to set the cross over frequency with r c and set the compensator zero with c c . using selected cr ossover frequency, f c , to calculate r c : i co_rms i l 12 ---------- = f p 1 1 2 c o r l ---------------------------------- - = f z 1 1 2 c o esr co ------------------------------------------------ = f p 2 g ea 2 c 2 g vea ----------------------------------------- - = f z 2 1 2 c 2 r 3 --------------------------------- - = f c 40 khz = r c f c v o v fb ---------- 2 c 2 g ea g cs ----------------------------- - =
AOZ1037 rev. 1.1 september 2010 www.aosmd.com page 11 of 14 where; f c is the desired crossover frequency. for best performance, f c is set to be about 1/10 of the switching frequency; v fb is 0.8v, g ea is the error amplifier transconductance, which is 200 x 10 -6 a/v, and g cs is the current sense circuit transconductance, which is 6.68 a/v the compensation capacitor c c and resistor r c together make a zero. this zero is put somewhere close to the dominate pole f p1 but lower than 1/5 of selected crossover frequency. c 2 can is selected by: the above equation can be simplified to: an easy-to-use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com . thermal management and layout consideration in the AOZ1037 buck regulator circuit, high pulsing current flows through two circuit loops. the first loop starts from the input capacitors, to the v in pin, to the lx pins, to the filter inductor, to the output capacitor and load, and then return to the input capacitor through ground. current flows in the first loop when the high side switch is on. the second loop starts from inductor, to the output capacitors and load, to the low-side nmosfet. current flows in the second loop when the low-side nmosfet is on. in pcb layout, minimizing the two loops area reduces the noise of this circuit and improves efficiency. a ground plane is strongly recommended to connect input capacitor, output capacitor, and pgnd pin of the AOZ1037. in the AOZ1037 buck regulator circuit, the major power dissipating components are the AOZ1037 and the output inductor. the total power dissipation of converter circuit can be measured by input power minus output power. the power dissipation of inductor can be approximately calculated by output current and dcr of inductor. the actual junction temperature can be calculated with power dissipation in the AOZ1037 and thermal impedance from junction to ambient. the maximum junction tem perature of AOZ1037 is 150c, which limits the maxi mum load current capability. please see the thermal de-rating curves for maximum load current of the AOZ1037 under different ambient temperature. the thermal performance of the AOZ1037 is strongly affected by the pcb layout. extra care should be taken by users during design process to ensure that the ic will operate under the reco mmended environmental conditions. the AOZ1037 is an exposed pad so-8 package. layout tips are listed below for the best electric and thermal performance. 1. the exposed pad lx pins are connected to internal pfet and nfet drains. connect a large copper plane to the lx pins to help thermal dissipation. 2. do not use thermal relief connection to the v in and the pgnd pin. pour a maximized copper area to the pgnd pin and the vin pin to help thermal dissipation. 3. input capacitor should be connected as close as possible to the v in pin and the pgnd pin to reduce the lx voltage over-shoot. this is especially impor- tant for v in >16v. 4. a ground plane is suggested. if a ground plane is not used, separate pgnd from agnd and connect them only at one point to avoid the pgnd pin noise coupling to the agnd pin. 5. make the current trace from the lx pins to l to c o to the pgnd as short as possible. 6. pour copper plane on all unused board area and connect it to stable dc nodes, like v in , gnd or v out . c c 1.5 2 r 3 f p 1 ---------------------------------- - = c c c o r l r 3 --------------------- = p total_loss v in i in v o i o ? = p inductor_loss i o 2 r inductor 1.1 = t junction p total_loss p inductor_loss ? () ja =
AOZ1037 rev. 1.1 september 2010 www.aosmd.com page 12 of 14 package dimensions, so-8 ep1 notes: 1. package body sizes exclude mold flash and gate burrs. 2. dimension l is measured in gauge plane. 3. tolerance 0.10mm unless otherwise specified. 4. controlling dimension is millimeter, converted inch dimensions are not necessarily exact. 5. die pad exposure size is according to lead frame design. 6. followed from jedec ms-012 symbols a a1 a2 b c d d0 d1 e e e1 e2 e3 l y | l1?l1' | l1 dimensions in millimeters recommended land pattern min. 1.40 0.00 1.40 0.31 0.17 4.80 3.20 3.10 5.80 ? 3.80 2.21 0.40 ? 0 ? d0 unit: mm nom. 1.55 0.05 1.50 0.406 ? 4.96 3.40 3.30 6.00 1.27 3.90 2.41 0.40 ref 0.95 ? 3 0.04 1.04 ref max. 1.70 0.10 1.60 0.51 0.25 5.00 3.60 3.50 6.20 ? 4.00 2.61 1.27 0.10 8 0.12 dimensions in inches d1 e1 e e3 e2 note 5 l1' l1 l gauge plane 0.2500 c d 7 (4x) b 3.70 2.20 2.87 2.71 5.74 1.27 0.80 0.635 e a1 a2 a symbols a a1 a2 b c d d0 d1 e e e1 e2 e3 l y | l1?l1' | l1 min. 0.055 0.000 0.055 0.012 0.007 0.189 0.126 0.122 0.228 ? 0.150 0.087 0.016 ? 0 ? nom. 0.061 0.002 0.059 0.016 ? 0.195 0.134 0.130 0.236 0.050 0.153 0.095 0.016 ref 0.037 ? 3 0.002 0.041 ref max. 0.067 0.004 0.063 0.020 0.010 0.197 0.142 0.138 0.244 ? 0.157 0.103 0.050 0.004 8 0.005
AOZ1037 rev. 1.1 september 2010 www.aosmd.com page 13 of 14 tape and reel dimensions so- 8 carrier tape so- 8 reel so- 8 tape leader/trailer & orientation tape size 12mm reel size ?330 m ?330.00 0.50 packa g e so- 8 (12mm) a0 6.40 0.10 b0 5.20 0.10 k0 2.10 0.10 d0 1.60 0.10 d1 1.50 0.10 e 12.00 0.10 e1 1.75 0.10 e2 5.50 0.10 p0 8 .00 0.10 p1 4.00 0.10 p2 2.00 0.10 t 0.25 0.10 n ?97.00 0.10 k0 unit: mm b0 g m w 1 s k h n w v r trailer tape 300mm min. or 75 empty pockets components tape orientation in pocket leader tape 500mm min. or 125 empty pockets a0 p1 p2 see n ote 5 see n ote 3 see n ote 3 feeding direction p0 e2 e1 e d0 t d1 w 13.00 0.30 w1 17.40 1.00 h ?13.00 +0.50/-0.20 k 10.60 s 2.00 0.50 g ? r ? v ?
AOZ1037 rev. 1.1 september 2010 www.aosmd.com page 14 of 14 part marking z1037pi fay part number code assembly lot code year & week code wlt fab & assembly location as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. this data sheet contains preliminary data; supplementary data may be published at a later date. alpha & omega semiconductor reserves the right to make changes at any time without notice. life support policy alpha & omega semiconductor products are not author ized for use as critical components in life support devices or systems.

▲Up To Search▲

Price & Availability of AOZ1037

	To Download AOZ1037 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .